Question $(3)$

$10$ Points

Complete the systemy architecture in VHDL model for the following logic circuit. Subsys$1$ and subsys $2$ are two instances of the component subsys used within the system.

systemv

entity s

port $($

$x1,x2,x3$ : in bit;

$Y$ : out bit$)$;

end entity;

architecture systemy $\_$arc of systemy is