Question $3(20\%)-$ Consider the MIPS CPU that was discussed in clsss$,$ where the

execution of each instruction goes through five different stages $($IF$,$ ID$,$ EXE, MEM,

WB$).$ The latency of each stage is shown in the following below.

In the following, you need to compare the pipelined CPU datapath with the single$-$

cycle CPU datapath when executing $20$ instructions.

Determine the clock cycle length and CPU speed $($frequency$)$ if the instructions

are executed using the single$-$cycle CPU datapath $($i$.$e$.$ without pipelining$).$

Determine the clock cycle length and CPU speed $($frequency$)$ if the instructions

are executed using the pipelined CPU datapath $($i$.$e$.$ five$-$stage pipeline$).$

Determine the speedup achieved by running the $20$ instructions on the

pipelined CPU datapath compared to the pipelined CPU datapath.