Question $3[25$ pts$]$

You are given two synchronous $3-$bit up counters with synchronous parallel load capability as shown below. $\backslash ($ L $\backslash )$ represents the load input $($load operation is performed when L$=1),$ CLK represents the clock input, D$2$D$1$D$0$ represent the data inputs and Q$2$Q$1$Q$0$ represent the count outputs. Assume that one of the counters is initialized to Q$2$Q$1$Q$0="000"$ and the other one is initialized to Q$2$Q$1$Q$0="001".$

Using these counters and some combinational logic $($e$.$g$.,$ basic gates like and$/$or etc.$)$ design a $6-$bit synchronous counter that counts in the following repeating pattern $($in decimal$)$:

$\backslash [$

$1\backslash$rightarrow $10\backslash$rightarrow $19\backslash$rightarrow $28\backslash$rightarrow $32\backslash$rightarrow $1\backslash$rightarrow $10\backslash$rightarrow $\backslash$cdots

$\backslash ]$

$($i$)$ Draw the circuit diagram. $[15$ pts$]$

$($ii$)$ Draw the timing diagram for each bit of the count output and load inputs for $6$ CLK cycles. $[10$ pts$]$

Hint: Work on $6-$bit unsigned $($binary$)$ representation of the decimal sequence given above.