QUESTION 3: (a) Design a synchronous counter using three negative-edged triggered JK flip-flops for the sequence listed below: 100, 010, 101, 000, 111 and repeats. Those undesired states go to 101 on the next clock pulse. Your design should include: i) State Transition Diagram by showing all possible states. [1 mark] ii) By referring to JK flip-flop Excitation Table, construct Circuit Excitation Table. [2 marks] iii) Perform Karnaugh Map simplifications for each of the negative-edged triggered JK flip-flops inputs. [3 marks) iv) Draw the synchronous counter. [1 mark]