Question $\backslash$#$3($computer architecture$)$ Let's consider dynamic scheduling. Consider a microarchitecture as shown in figure below. Assume that the arithmetic$-$logical units $($ALUs$)$ can do all arithmetic ops $($MULTD$,$ DIVD, ADDD, ADDI, SUB$)$ and branches, and that the Reservation Station $($RS$)$ can dispatch at most one operation to each functional unit per cycle $($one op to each ALU plus one memory op to the LD$/$ST$).$

Suppose all of the instructions from the sequence below are present in the RS$,$ with no renaming having been done. Highlight any instructions in the code where register renaming would improve performance. $($Hint: Look for read$-$after$-$write and write$-$after$-$write hazards. Use the functional unit latencies in figure below.$)$

Latencies beyond single cycle