Question: Question 3 Consider the computer of Lab 4, the architecture of which is described in Figure 1 and Tables 1, 2, 3, 4, and 5.

 Question 3 Consider the computer of Lab 4, the architecture of

Question 3 Consider the computer of Lab 4, the architecture of which is described in Figure 1 and Tables 1, 2, 3, 4, and 5. The instruction type is determined by the two most significant bits of the 8- bit register IR, as follows: Xo = IR(7)' IR(6)' denotes a memory-reference instruction (MRI) in direct addressing mode; X1 = IR(7) IR(6) denotes a register-reference instruction (RRI); and X2 = IR(7) IR(6) denotes a memory-reference instruction (MRI) in indirect addressing mode. The control unit of this computer I'd built around a sequence counter (SC). The sequence counter can be inxremented o cleared synchronously. SC is incremented wit every positive clock transition, unless its CLR- SC input is active. Derive the transition table and design team sequence counter using jk flip flops. Question 3 Consider the computer of Lab 4, the architecture of which is described in Figure 1 and Tables 1, 2, 3, 4, and 5. The instruction type is determined by the two most significant bits of the 8- bit register IR, as follows: Xo = IR(7)' IR(6)' denotes a memory-reference instruction (MRI) in direct addressing mode; X1 = IR(7) IR(6) denotes a register-reference instruction (RRI); and X2 = IR(7) IR(6) denotes a memory-reference instruction (MRI) in indirect addressing mode. The control unit of this computer I'd built around a sequence counter (SC). The sequence counter can be inxremented o cleared synchronously. SC is incremented wit every positive clock transition, unless its CLR- SC input is active. Derive the transition table and design team sequence counter using jk flip flops

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