Question$3$

Define the term $"$RC delay" in the context of VLSI interconnect. How does increasing wire length

and capacitance affect RC delay? What strategies can be employed to mitigate this delay?

Question $4$

Discuss the impact of wire resistance on VLSI interconnect. How can resistance be minimized,

and what are the consequences of excessive resistance in on$-$chip wiring?

Question $5$:

What did you like the most about this course $($easy $10$pt$,$ short summary$)$