Question $4(3+3+3$ marks$)$

The following FSM has been designed with an initial clock period is $9$ ns $.$ The D$-$FF have the following parameters: $t_{cCQ}=2ns,t_{pcQ}=3ns,t_{\text{s}\text{e}\text{t}\text{u}\text{p}}=1ns$ and $t_{\text{h}\text{o}\text{l}\text{d}}=5ns.$ The combinatorial blocks have the following timing parameters: CL$1$: $t_{cd}=2ns,t_{pd}=3ns$; CL$2$: $t_{cd}=4ns,t_{pd}=5ns.$ A$,$ B and C are node names to track the signal.

Is there a timing violation in the circuit? If so what is it and on what path does it occur?

B$-$CL$1-$A $-$ Holdtime

violation

Assume that you have a non$-$inverting buffer with $t_{cd}=2ns,t_{pd}=4ns.$Draw the new circuit diagram showing how these may be used to fix the timing violation.

Add $1$ buffer in the path