QUESTION 4 (a) Identify two advantages of using programmable logic over discrete digital logic ICs in digital systems design. (2 marks) (b) Explain the reason for including Design for Testability (DfT) strategies in the design of digital systems. (2 marks) (c) Show the Mealy Model state diagram for a synchronous sequential circuit which has two inputs X1 and X2 and one output z. The output will be HIGH (1) whenever both input sequence on X1 and X2 are 0011 at the same time. The output will be HIGH (1) during the last bit of the sequence. (6 marks) (d) A seven-segment display, with segments named 'a' through 'g', is shown in Figure 3 and the corresponding display for decimal digits 0 to 9 is shown in Figure 4. Develop a Verilog code for a BCD to seven-segment decoder with an additional input, 'blank', that overrides the BCD input and causes all segments not to be lit Invalid codes are represented by a (5 marks) Rajah 3 (Figure 3) 0123456789 Rajah 4 (Figure 4) QUESTION 4 (a) Identify two advantages of using programmable logic over discrete digital logic ICs in digital systems design. (2 marks) (b) Explain the reason for including Design for Testability (DfT) strategies in the design of digital systems. (2 marks) (c) Show the Mealy Model state diagram for a synchronous sequential circuit which has two inputs X1 and X2 and one output z. The output will be HIGH (1) whenever both input sequence on X1 and X2 are 0011 at the same time. The output will be HIGH (1) during the last bit of the sequence. (6 marks) (d) A seven-segment display, with segments named 'a' through 'g', is shown in Figure 3 and the corresponding display for decimal digits 0 to 9 is shown in Figure 4. Develop a Verilog code for a BCD to seven-segment decoder with an additional input, 'blank', that overrides the BCD input and causes all segments not to be lit Invalid codes are represented by a (5 marks) Rajah 3 (Figure 3) 0123456789 Rajah 4 (Figure 4)