Question 4: Assume that the base CPs for a pipelined Datapath on a single core system is 1. Note that this does NOT include the overhead associated with cache missesin Profiles of a benchmark suite that was run on this single care chip with an Ll cache suggest that for every 10,000,000 accesses to the cache, there are 308,752 cache misses. - If data is found in the cache, it can be accessed in 1 clock cycle, and there are no pipe stalls - If data is not found in the cache, it can be accessed in 10 clock cycles Now, considera multi-core chip wystem where each core has an equivalent L1 cacher - All cores references a common, centralised, shared memory - Potential conflicts to shared data are resolved by snooping and an MST coherency protocol Benchmark profiling obtained by running the same benchmark suite on the multi-core system sugests that, on average, there are now 452,977 misses per 10,000,000 accesses. If data is found in a cache, it can still be accessed in 1 clock cycle. On average, 14 cycles are