Question $6(10$ points$)$

Design the controller for the paraller to serial conversion of $4-$bit data using the shift register in Question $5.$ The controller operation is described with the ASM chart below. The controller has input ST for starting the conversion process and two outputs: Enable $($E$)$ for enabling loading$/$shifting data in the register with a gated clock and Load $($L$)$ for controlling the register mode $($load vs shift$).$ The register should output data with the most significant bit first. The master clock runs continuously. Upon initialization the system enters the idle state and returns to the idle state as long as $\backslash (\backslash$mathrm$\{$ST$\}=0\backslash ).$ With input $\backslash (\backslash$mathrm$\{$ST$\}=1\backslash )$ the controller enters the load state with asserted output Load: the register operating mode load is selected, the gated clock for triggering the D$-$flip$-$fllps of the register is enabled. In the following clock cycles the gated clokc is enabled, tbe data bits are being shifted out $($states Sh$1$ to Sh$4)$ then the system returns to the idle state.

a$)$ Perform state assignment $($your choice$)$

b$)$ Obtain D$-$flip$-$ flop input excitation equations, equations for the output forming logic, gated clock, implement the equations with D$-$flip$-$flops, any number of $2-$to$-1$ multiplexers and inverters.

c$)$ Obtain the complete system schematic including both the controller and the shift resister. Obtain the gated clock for the register synchnization from the master clock and Enable.