Question $7(10$ points$)$

Design the synchronous system for generation of $6$ non$-$overlapping timing signals $\backslash (\backslash$mathrm$\{$T$\}0,\backslash$ldots $\backslash$mathrm$\{$~T$\}5\backslash )$ as shown below. Use a Johnson counter approach with $3$ D$-$flip$-$flops and a state decoder to form the timing signals.

a$)$ Obtain the state diagram including both used and unused states. A self$-$correction is not required.

b$)$ Sketch the schematic including the state decoder. Use the shift register in Question $5$ as the building block and any logic gates.