Question $7(12$ marks$)$

Consider the following circuit. The input NAND has an input capacitance of $10$ units. The output capacitance is $90$ units where $3\mathrm{.}5$ units denotes the gate capacitance of the smallest inverter in the technology sized $1\mathrm{.}5/1.$ Assume that the polarity of the output is not important.

Calculate the path effort in the critical path of the circuit.

$f=354\mathrm{.}82$

hat$(f)=7\mathrm{.}079,D=29\mathrm{.}237$

Size the critical path for minimum delay. Show the transistor le ${?}^1$