Question $7.[12$ points$]$ Edge Sensitive and Level Sensitive Circuits.

Background: It$$s common in digital systems to lower the power consumption of a device by

lowering the voltage. Lowering the voltage provides energy savings which allows devices to run

for longer on battery or to save money by using less electricity. Occasionally when the voltage is

lowered timing errors can occur in a circuit, as digital circuit components react slower when the

voltage is lowered. This question will look at timing errors in an $8-$bit integer multiplication unit.

The multiplication unit in this question takes two $8-$bit vector inputs, x$[7$:$0]$ and y$[7$:$0],$ and

has a single $16-$bit output mul$[15$:$0].$ x and y are loaded into the multiplier on the rising edge

of the clock, and then the result is output on the next rising edge. This behavior is shown in

the timing diagram in the first two clock cycles. At time $1,$ x and y Then, at time

$3,$ mul This is result of $51,$ which were the inputs loaded into x and y the previous clock cycle.

The voltage to this multiplication unit has been adjusted to lower the energy that the device

uses, and this causes the multiplication unit to have timing errors. When timing errors occur the

multiplication unit delivers the result half of a clock cycle late, or in the middle of the clock cycle.

As the module is expected to provide the solution at the rising clock edge, this late data will cause

an error in the system.

A timing error is shown in the diagram starting at time $9.$ The multiplication unit failed to

produce an output of $812$ at the correct time, and ended up producing the result, $96,$ half a clock

cycle late. A situation where multiple errors occur in a row is shown from time $14$ to time $17.$

Your task: Your task is to develop a diagram for a module that outputs a one$-$bit error signal

when a timing error occurs. This is the error signal shown in the timing diagram. The error signal

is triggered when a change in mul is on the negative edge of the clock. When this mid$-$clock cycle

change is detected, error goes high until the rising edge of the next clock cycle. Then error goes

low until another negative edge clock change in mul is detected.

Your module must take mul$[15$:$0]$ and clk as inputs and must produce error as an output.

You can assume that any latch, flip$-$flop, or basic logic gate $($AND$,$ OR$,$ NOT, XOR$)$ is available

to be used in your error detection module. Draw your module on the following page $(8$ points$)$ and

briefly explain $($in writing or with a timing diagram$)(4$ points$)$ how and why your circuit produces

the error signal.