Question $9.(20$ points$)-$ Spice Simulation

Complete the following SRAM circuit optimization procedure. Submit your source codes of the HSpice netlist and stimulus, simulation results, and screenshots of your simulation.

$($Refer to the lab sessions $($Labs $2,3,4$ and $8),$ and Lec$21$ and Lec$22)$

$1.$ Design $6$T SRAM cell $($see Fig. $1)$ in Virtuoso and simulate reading and writing operations. $\backslash ((\backslash )$ Vdd $\backslash (=1\mathrm{.}1\backslash$mathrm$\{$v$\}\backslash ),$ Capacitance $\backslash (=1\backslash$mathrm$\{$f$\})\backslash )$

$1)$ Create a schematic and netlist of the $6$T SRAM cell.

$2)$ Plot the Reading $0$ and $1$ operation $($Please attach the CosmosScope result$).$

$3)$ Plot the Writing $0$ and $1$ operation $($Please attach the CosmosScope result$).$

$2.$ Considering the delay, repeat the simulation of reading and writing operations and optimize $6$ T SRAM cell circuit.

$1)$ Optimize each transistor width size to minimize reading and writing operation delays. Fill out the below table using optimized width sizes that you obtained from the simulations. $($Hint: Use the given width sizes $($Size $1(90$nm$),$ Size $2(180$nm$),$ Size $4\backslash ((360\backslash$mathrm$\{$~nm$\})\backslash ),$ Size $\backslash (6(540\backslash$mathrm$\{$~nm$\})\backslash )$ and Size $\backslash (8(720\backslash$mathrm$\{$~nm$\})\backslash )),$ and simulate your circuit to find the minimum delay$)$

$*$Note: $1-90$nm$,2-1800$nm$,4-360$nm$,6-540$nm$,8-720$nm

$2)$ Plot the Reading $0$ and $1$ operation $($Please attach the CosmosScope result$).$

$3)$ Plot the Writing $0$ and $1$ operation $($Please attach the CosmosScope result$).$

$4)$ Compare the measurement results using HSpice. $($Please attach screenshots of your delay measurement result $(.$mt$0$ file$))$

$3.$ Explain 'read stability' and 'writability' by using HSpice simulation.