QUESTION ONE

a$)$ Draw a functional block diagram and construet the compressed function table of the $74$LS$138$ chip whic is a $3$ to $8$ decoder with low active outputs and three enable controls, two of them low active $($en$0\_$bar anc en$1\_$bar$)$ and one high active $($en$2).$

b$)$ Write down the complete and compact VDHL behavioural description of the chip including an entity header and architecture body. Assume a total propagation delay through the chip to the outputs of $10$ ns $.$

c$)$ The WAIT statement in VHDL can have up to three clauses as given in the following BNF rules:

$```$

wait$\_$statement ::$=$ WAIT $[$sensitivity$\_$clause$]$

$[$condition$\_$clause$]$

$[$timeout$\_$clause$]$ ;

sensitivity$\_$clause ::$=$ ON sensitivity$\_$list

condition$\_$clause ::$=$ UNTIL boolean$\_$expression

timeout$\_$clause ::$=$ FOR time$\_$expression

$```$

Explain the semantics of the statement starting with the WAIT statement without any of the clauses, through all the combinations of included clauses to one which includes all the three clauses.

QUESTION TWO

a$)$ Figure Q$.2$ shows the internal logic circuit diagram of a positive level triggered $\backslash (\backslash$boldsymbol$\{$D$\}\backslash )$ type flip flop. Assumin ENTITY descriptions of $2$ input and $3$ input NAND gates having been already included in a library, write down the complete structural description of the $\backslash (\backslash$boldsymbol$\{$D$\}\backslash )$ type flip flop. Assume the entity boundaries given in the diagram with the formal ports represented by the rectangular black boxes in the diagram.