Ranging detection circuit: $($make sure to draw any necessary diagrams$/$circuits$/$ k$-$maps$)$

a$.$ Design a four$-$input detector circuit whose output is equal to $1$ when the number of $1\text{'}$s modulo $3$ is $0.$

b$.$ Using exclusive OR gates, derive a four$-$bit binary to gray code converter.

c$.$ Using a case statement, write the pseudo code for the circuit in part $($b$).$ You may use behavioral Verilog.