rapid digital systems prototyping

QUESTION 2 (a) State two (2) necessary components for creating and executing a Verilog test bench. [4 Marks] [CO2,PO2,C2] (b) Explain briefly, why a Verilog test bench cannot be synthesized? [2 marks] [CO2,PO2,C2) (c) Write a Verilog test bench and obtain the binary output for the module given in Figure 3. [14 Marks) (CO2,PO2,C3] module Q2 (A, B, C, Out1, Out2): input A,B,C output Out1, Out2; assign Out1 = ( A B ) C: assign Out2 - C&(AWB) ( AB): endmodule