Read the problem specification posted below this assignment on the Moodle course page. Then, write a VHDL architecture for the entity below:

entity fixed$\_$point$\_$divider is

port$($ a$3,$a$2,$a$1,$a$0$: in bit;

b$2,$b$1,$b$0$: in bit;

s$,$w$2,$w$1,$w$0,$f$1,$f$2,$f$3,$f$4$: out bit$)$;

end fixed$\_$point$\_$divider;

Directions:

Implement the circuit using only VHDL predefined logic operators $($e$.$g$.,$ not, and, or$,$ nand, nor, xor, xnor$)$

You're not required to simplify the function. However, doing so may make it easier to implement.

A testbench and other resources are posted below this assignment. Use the testbench provided to test your code.

Credit will be awarded based on how many of the test cases in the testbench pass.

Copy$/$paste the VHDL code for your final design in the box below or upload a text file.