Real$-$Time Parity Bit Generator $($PG$4)$ Design

PG$4$ Block Diagram and Description.

The block diagram for PG$4$ is denisted helow.

PG$4$ operates with the following specifications:

PG$4$ is a synchronous system, synchronized with the rising edge.

When reset is $0$ and enable is $1,$ the values of $P_{in}$ are stored up to a maximum of $4.$

$P_{\text{o}\text{u}\text{t}}$ outputs $0$ if the number of $1\text{'}$s in the stored $P_{in}$ values is even, and outputs if it is odd.

When reset is $0$ and enable is $0,PG4$ maintains its stored value.

When reset is $1,$ the stored values are initialized to $0000.$

When reset is $1,$ the PG$4$ doesn't store any values.