References Mailings Review View Table Design Layout + Share No Spacing HeadingTStyles Pane 5. [12 points] We examine how pipelining affects the clock cycle time of the processor. Assume that individual stages of the data-path have the following latencies: IF 250 ps ID 350 ps EX MEM WB 200 ps Also, assume that individual stages of the data-path have the following latencies: ALU BEQ 20% Sw LW 20% ai Vo ng SC (a) What is the clock cycle time in a pipelined and non-pipelined processor? b) What is the total latency of an LW instruction in a pipelined processor and a non- pipelined processor? (c) If we can split one stage of the pipelined data-path into two new stages, eachtwith half latency of the original stage, which stage would you split and what is the new cycle time of the processor? (d) Assuming that there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming that there are no stalls or hazards, what is the utilization of the write register port of the "Registers" unit? (t) What are the values of all inputs for the "Registers" unit? f w