Register File HLSM Inputs Btn0 (bit), Btn1 (bit), Btn2 (bit), Switch (8 bits) Outputs HexDisp (16 bits), W Addr (4 bits), R Addr (4 bits) Local Storage RegFile(16) (8 bits), W AddrReg (4 bits), R AddrReg (4 bits), Sum Reg (16 bits), HexDispReg (16 bits) Btn2' Btn2' Btn1 Btn0' Ld Addr Reg Btn0 Idle W AddrReg Switch(7 4) Disp RegFile R AddrReg Switch(3 0) HexDispReg Btn1 Btn0' Btn2 RegFile(W AddrReg) Write Data RegFile(R AddrReg) Btn2 Btn1' Btn0' RegFile(W AddrReg) Switch(7 0) Disp Sum R AddrReg 15 R AddrReg 15 HexDispReg SumReg Sum Wait1 Init Sum R AddrReg 0 SumReg 0 SumReg SumReg RegFile(R AddrReg) R AddrRegR AddrReg 1 a Create a datapath for the HLSM and draw its circuit diagram b Draw a system interconnect diagram showing the controller and datapath blocks with all inputs, outputs, and interconnections shown and labeled c Draw the FSM state diagram for the Controller, with fully labeled transition conditions and outputs, d Create your first draft of the VHDL code for the datapath and controller modules

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Question: Register File HLSM Inputs: Btn0 (bit), Btn1 (bit), Btn2 (bit), Switch (8 bits) Outputs: HexDisp (16 bits), W_Addr (4 bits), R_Addr (4 bits) Local

Register File HLSM Inputs: Btn0 (bit), Btn1 (bit), Btn2 (bit), Switch (8 bits) Outputs: HexDisp (16 bits), W_Addr (4 bits), R_Addr (4 bits) Local Storage: RegFile(16) (8 bits), W_AddrReg (4 bits), R_AddrReg (4 bits), Sum Reg (16 bits), HexDispReg (16 bits) Btn2' Btn2' Btn1 Btn0' Ld_Addr_Reg Btn0 Idle W_AddrReg:= Switch(7:4) Disp_RegFile R_AddrReg Switch(3:0) HexDispReg := Btn1*Btn0' Btn2 RegFile(W_AddrReg) & Write_Data RegFile(R_AddrReg) Btn2*Btn1'*Btn0' RegFile(W_AddrReg) := Switch(7:0) Disp_Sum R_AddrReg=15 R_AddrReg

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