Reorganize the code sequence in the figure below to reduce the number of NOOPs.

Load TAM Load BM Add ICTA + B Store MIC Branch X IED IED IE IED IE Load TAM IED Load BM I ED Add C = A + B 1 E Store MIC IED Branch X I E NOOP IE (a) Sequential execution (b) Two-stage pipelined timing Load TAM Load BM NOOP Add TC TA + B Store MIC Branch X NOOP IED IED IE E IED IE IE Load TAM Load rBM NOOP NOOP Add CrA + TB Store MC Branch X NOOP NOOP IEED IEED TEJE IEE2 I EE2 IEE IEE IEE2 IEE (c) Three-stage pipelined timing (d) Four-stage pipelined timing Figure 15.6 The Effects of Pipelining Load TAM Load BM Add ICTA + B Store MIC Branch X IED IED IE IED IE Load TAM IED Load BM I ED Add C = A + B 1 E Store MIC IED Branch X I E NOOP IE (a) Sequential execution (b) Two-stage pipelined timing Load TAM Load BM NOOP Add TC TA + B Store MIC Branch X NOOP IED IED IE E IED IE IE Load TAM Load rBM NOOP NOOP Add CrA + TB Store MC Branch X NOOP NOOP IEED IEED TEJE IEE2 I EE2 IEE IEE IEE2 IEE (c) Three-stage pipelined timing (d) Four-stage pipelined timing Figure 15.6 The Effects of Pipelining