Requirement:

In Verilog, Let's implement the circuit below that processes a series of instructions in ROM:

The ALU block can perform the following operations encoded as follows:

The result of a NOP is always $0.$ Also, NOP is considered to be the default value. The flags have the following

meaning: The flags have the following meaning:

ROM instructions:

Requirement

To implement the blocks above.

To implement a top file that instantiates the modules created in the previous point.

Create a test file that:

a$.$ Endorses the entire scheme

b$.$ To generate a clock with the frequency of $1MHz.$ The 'timescale directive will be used.

Simulate the circuit, attach a screenshot of the simulation and explain the operation for one of the cases.

To explain why some of the operations provided by the ROM are not executed and to propose a solution to solve

this problem.