Requirements: 1. Submission should include System Verilog code files along including the test-bench. Include the top-level module with this format. module lab5(input clk, reset, output logic [3:0] OPCODE, output logic [1:0] State, output logic [7:0] PC, Alu_out, W_Reg, output logic Cout, OF ); This should be instantiated in your test bench. 2. Alog file in csv format written during the execution step, it should contain (use this order) PC, IR, OPCODE, RA, RB, RD, W_Reg, Cout, OF Use these headings on your columns. This log file is critical to show that your MCU works and will be compared against our expected result. It is important that you use this exact format. Write the numbers in this log file in hexadecimal format. Include vour log file in your submission. Note: it is quite easy to do this in the test bench, but how to de that may not occur to you. You can write to a log file not only in the test bench but in any module. In any case write to the log file at the end of the execution cycle. If put it in a synthesizable module (that is not the test bench) comment the lines writing the log file for physical validation on the prototype board, because they will not compile and will be an error in Quartus. Just be sure not to change the format of the L.ab5 module given above. 3. Simulate the design first using a testbench. Submit the waveforms showing the PC, OPCODE, and W_Register for the first 5 values of PC, and then a separate screen grab of these values during the last 5 values of PC. 4. Implement on vour prototype board. Submit the Lab5.sof file. For programming your board, your top-level module should look like this. Include it in your submission. This module should contain an instance of the module in (1) above. This is a requirement of the lab