RISCV Computer Architechture $1.($n the first design, the brferent processor designs for the purpose of performance $($execute$)$ stage, while in the second design, the branch condition and target address are resolved stauge, the system clock cycle time is increased by $10\%.$ Assume that $20\%$ of all the instructions executed by the processor are branch instructions, of which $70\%$ are taken branches.

a$)$ The CPI of both the processors is $1\mathrm{.}2$ when only the effect of data hazards is considered. Evaluate the new CPI for both the processors, accounting for the effect of control hazards in addition to the data hazards.

b$)$ Furthermore, find out which of the two processor designs is more efficient.