$S_n=A_n^{\text{'}}{B}_n^{\text{'}}{C}_n+A_n^{\text{'}}{B}_n{C}_n^{\text{'}}+A_n{B}_n^{\text{'}}{C}_n^{\text{'}}+A_n{B}_n{C}_n$

$C_{n+1}=A_n{B}_n+A_n{C}_n+B_n{C}_n$

Questions:

Count how many $2-$input gates are required to implement the minimum SOP of $S_n($above$),$ including $3$ NOT gates.

Count how many $2-$input gates are required to implement the minimum SOP of $C_{n+1}($above$).$

If you built both circuits, how many gates would you need for one full adder? What about four full adders?

Prove that $S_n=A_{n}o+B_{n}o+C_n.$ Show your work. How many $2-$input gates are required to implement this?

Prove that $C_{n+1}=A_n{B}_n+C_n(A_{n}o+B_n).$ Show your work. $($Hint: try expanding $A_n+B_n{A}_n^{\text{'}}{B}_n+A_n{B}_n^{\text{'}}+A_n{B}_n).$ How many $2-$input gates are required to implement this?

Can any gates be shared between the new expressions for $S_n$ and $C_{n+1}?$ If they share, how many $2-$input gates are required to implement one full adder using these circuits?

I just need $5$ and $4$