Section 6.1-Decoders 6.1.1 Design a 4-to-16 one-hot decoder by hand. The block diagram and truth table for the decoder are given in Fig. 6.1. Give the minimized logic expressions for each output (i.e., Fo. F1, .., F15) and the full logic diagram for the system. 4-to-16 One-Hot Decoder F1 F15 F14 F12 F10 Fe Fs F F2 Fo 15 13 F11 0000 0000000 0000 0 0 00 1 0 00 1 000 0 0 000 0 0 0 0 0 0 1 0 00 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 001 1 0 0 0 00 0 0 0 0 0 0 0 10 0 0 0 100 0 0 0 0 0 00 0 0 0 0 1 00 00 01 01 0 0 0 0 0 00 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 00 1 0 0000 0 0 1 1 1 0 00 0000 0 1 0 000000 1000 000 0000 1 0 00 000 0 0 1 00 1 00 0 0 0 0 1 0000 0000 0 1 010 0 0 0 0010 000 0000 0 0 1 0 1 100 0 0 100000000000 11 000 0 0 1 0000 0000000 0 1101 001 0 0 00 000 0 0000 0 1 1 1 0 0 10 0000 0 0 0 0000 0 0 1 1 1 1 1 00 00000000 0 0 0 0 0 Fig. 6.1 4-to-16 One-Hot Decoder Functionality