Question: Select the statement that best describes the two possible output states of a flip-flop. The Q output is LOW and the output is LOW. The
Select the statement that best describes the two possible output states of a flip-flop.
The Q output is LOW and the output is LOW. |
The Q output is LOW and the output is HIGH. |
The Q output is HIGH and the output is LOW. |
The Q output is HIGH and the output is HIGH. |
| Both B and C |
Which of the following is the most common use of flip-flops?
| Pulse steering circuits |
| Switch debouncing |
| Storage registers |
| Combinatorial logic arrays |
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Question 31 pts
How many shift pulses would be required to serially shift the contents of one six-stage register to another?
| 8 |
| 7 |
| 5 |
| 6 |
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Question 41 pts
The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle indicates:
| the FF is edge-triggered and can only change states when the clock goes from 1 to 0. |
| the FF is edge-triggered and can only change states when the clock goes 0 to 1. |
| the FF is level active and can only change states when the CLOCK = 1. |
| the FF is an active LOW device and can only change states when the CLOCK = 0. |
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Question 51 pts
A negative-edge-triggered J-K flip-flop is presently in the CLEAR state. Which of the following input conditions will cause it to change states?
| CLK = PGT, J = 1, and K = 0 |
| CLK = NGT, J = 1, and K = 0 |
| CLK = PGT, J = O, and K = 1 |
| CLK = NGT, J = O, and K = 1 |
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Question 61 pts
The difference between a D-latch and an edge-triggered D-type flip-flop is that the latch:
| always "latches" the Q output to the D input regardless of other inputs. |
| triggers on either the rising or falling edge of an ENABLE signal rather than the CLK input logic level. |
| always "latches" the Q output to the complement of the D input regardless of other inputs. |
| is controlled by the logic level at its ENABLE input rather than a CLK transition. |
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output is LOW.
output is HIGH.
output is LOW.
output is HIGH.