Select the statement that is not correct about the MIPS pipelined processor. Group of answer choicesThe MIPS pipelined control approach determines all control line values during an instruction's $1$st clock cycle $($fetch stage$).$ Processor accesses the Memory $($Instruction or Data$)$ during two stages of Fetch and Memory Access. The length of clock cycle in a pipelined processor is determined by longest pipeline stage.During instruction decode stage, the instruction's fields are converted into datapath control signals, and simultaneously the register file $($Reg$)$ is read.