setAssociative.v: A digital circuit that implements the read$-$hit logic of a set associative cache $($hard$)(25$ points$)$

Your task

Your task in this assignment part is to create a digital circuit that decides whether a read address given to a cache is a read$-$hit, and if it is$,$ provides the single$-$byte data block as output. The cache in question is a E$=2$ way set$-$associative cache, with m$=3$ bit addresses, t$=1$ bit tags, s$=1$ bit set indices for S$=2$ sets, b$=1$ bit block offsets such that data blocks are two bytes to support data locality. The total capacity of the cache is S$*$E$*$B $=2*2*2=8$ bytes.

Input format

The interface to the cache logic is given in setAssociative$\_$provided.v$.$ The address to be read from is given to the cache in read$\_$address. The state of the cache $($stored in SRAM sequential logic$)$ is recorded in the rest of the inputs.

Output format

The circuit has two outputs. The output "read$\_$hit" is true if and only if the address to be read matches the tag in either line of the correct set, and that said line is valid. The output "read$\_$byte" contains the $8-$bit block data of the line if the address is a read$-$hit, otherwise its value is ignored.

Test cases and expected answers

The inputs for each test case are recorded in the tests$/$ directory. Corresponding expected answers are recorded in the answers$/$ directory.

Hints

The $2-$bit comparator from part $1$ should be useful. The demonstration code for the digital logic for a directMapped cache in the directMapped$/$ directory should also be useful. The logic for this part can be completed in under $450$ lines of code.