Seven-segment decoder. A seven-segment decoder is a combinational circuit with a four-bit input a and a seven-bit output q. Each bit of q corresponds to one of the seven segments of a display according to the following pattern: 4 2 That is, bit 0 (the LSB) of q controls the middle segment, bit 1 the upper left segment, and so on, with bit 6 (the MSB) controlling the top segment. Seven-segment decoders are described in more detail in Section 7.3. A full decoder decodes all 16 input combinations -approximating the letters A - F for combinations 10-15. A decimal decoder decodes only combinations 0-9, the remainder are don't cares. a) Design a sum-of-products circuit for segment 2 of the full seven-segment decoder b) Design a sum-of-products circuit for segment 4 of the decimal seven-segment decoder. c) Design a product-of-sums circuit for segment 0 of the full seven-segment decoder. d) Design a product-of-sums circuit for segment 5 of the decimal seven-segment decoder