Show how the following four consecutive instructions move through each stage of the five stage pipeline. The five stages are Instruction Fetch(IF), Decoder (DR), ALU, Data Memory (DM), and Register Write (RW). You may assume that the DR stage also does the register read. Make sure the decode stage does not advance an instruction through the pipeline unless all data dependences are correctly resolved.

I1: add $s1, $s2, $s3 I2: lw $s4, 8($s2) I3: add $s5, $s4, $s1 I4: sw $s5, 8($s2)