Show the needed changes to the above single cycle processor design of MIPS shown below to support the load upper immediate LUI instruction of the MIPS instruction set architecture.

strction 25-0ShiftJump address [31-0 left 2 26 28 PC+4 [31-28) ALU Shift left 2 Branch Instruction [31-261 Control MemtoR Instruction [25-21] register 1 Instruction [20-16] data 1 Registers Read data 2 Zero ALU ALU 31-0] Instruction data x nstruction [15-111 Write Write data 16 extend control nstruction [5-0 strction 25-0ShiftJump address [31-0 left 2 26 28 PC+4 [31-28) ALU Shift left 2 Branch Instruction [31-261 Control MemtoR Instruction [25-21] register 1 Instruction [20-16] data 1 Registers Read data 2 Zero ALU ALU 31-0] Instruction data x nstruction [15-111 Write Write data 16 extend control nstruction [5-0