Show why Fig 5.8 would have problems with a instruction set that included autoincrement mode such as ADD R3,(R4)+

Stage 5 file Stage 2 Stage 3 Stage 4 MuxY RY Stage 5 Figure 5.8 Datapath in a processor Address C Immediate value MuxR RM Return address Memory Stage 5 file Stage 2 Stage 3 Stage 4 MuxY RY Stage 5 Figure 5.8 Datapath in a processor Address C Immediate value MuxR RM Return address Memory