Shown below is a PMOS current mirror with VDD = 1.8 V, Ibias = 150 A,...
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Shown below is a PMOS current mirror with VDD = 1.8 V, Ibias = 150 A, R = 2 k2, and all transistors sized (W/L) = 18 m/0.2 m and having the device parameters for the 0.18-m CMOS process. Ignore body effect. a. With V = 1 V are all transistors in saturation? b. What is the maximum voltage that can appear at V. while still keeping all transistors in saturation? c. Assuming all transistors are in saturation, what is the small-signal output resistance seen looking into the drain of Q4? R Ibias VDD Vo Shown below is a PMOS current mirror with VDD = 1.8 V, Ibias = 150 A, R = 2 k2, and all transistors sized (W/L) = 18 m/0.2 m and having the device parameters for the 0.18-m CMOS process. Ignore body effect. a. With V = 1 V are all transistors in saturation? b. What is the maximum voltage that can appear at V. while still keeping all transistors in saturation? c. Assuming all transistors are in saturation, what is the small-signal output resistance seen looking into the drain of Q4? R Ibias VDD Vo
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Related Book For
Analysis and Design of Analog Integrated Circuits
ISBN: 978-0470245996
5th edition
Authors: Paul R. Gray, ? Paul J. Hurst Stephen H. Lewis, ? Robert G. Meyer
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