Simulate an Error Correction Code $($ECC$)($Hamming Code$)$

Given that memory system designs are more susceptible to bit errors than logic circuits, it is more

common to include some form of error detection of memory circuits. A common approach is to

use parity. Recall that parity that parity involves counting the number of $1$ bits in a code word and

setting the parity bit to $1$ or $0$ to ensure that the total number of $1$ bits is even. In the case of

memory architectures, we would like to be able not only to detect but also to correct one bit flipped.

One scheme is to use a form of error correcting code $($ECC$)$ known as a Hamming code, that is$,$ a

code that allows us to correct a single bit flip within a Code word. If our code word has $N$ bits, we

need $lo{g}_2(N+1)$ additional check bits for the EEC. For example, if we have $8$ data bits, we need $4$

check bits, giving a total of $12$ bits. When we write to a memory location, the check $($parity$)$ bits

are computed from the values of the data bits, and the entire ECC word is written to the memory

location. When the memory location is read, the entire ECC word is read. We recompute the values

of the parity bits from the data ECC bits and compare them, using a bit$-$wise exclusive OR$,$ with

the parity bits read from the memory. If the comparison results in $0000,$ the recomputed parity bits

match the read parity bits. However, if one of the stored ECC bits $($either a data bit or a parity bit$)$

is flipped from the original, the comparison result will be other than $0000.$ It turns to be the binary

location $($index$)$ of the ECC bit that has flipped. Thus, we can correct the error by flipping the

position $($indexed$)$ bit back.

The Project: Write VHDL and Simulate the ECC Hamming code for an $8-$bit

Word data.

Requirements:

Given an $8-$bit word data, you code must produce $12-$bit ECC word after adding the parity bits.

how to create code using aldec VHDL