SIMULATION WORKS AND EXERCISES 1. Shift-Add-3 Module Each group are required to write the Verilog code of the shift-add-3 module: Boolean Refer to the table at the end of this document to see which mode is assigned to your group. Suggested module declaration: module ShiftAdd3 (input [3:0] theBin, output [3:0] theAdd3); Declare ports as reg if necessary. 1 Assigned for our group Group group Shift-Add-3 Mode Boolean TESTER 4, 37, 145 DELIVERABLES Your group has to submit the simulation and discussion: 1. The 4 Verilog code as requested under Simulation Work and Exercises above. 2. Discussion with regards to the code and simulation results