solution and explain why you solution like it specipclyyy q$2$

Q$1)(14$ points: $\backslash (9+5\backslash ))$

a$)$ Show the detailed block diagram for the FPGA's LUT that implements the following function

$\backslash [$

F$($A$,$ B$,$ C$,$ D$)=$A$^\{\backslash$prime$\}$ B D$+$C$^\{\backslash$prime$\}$ D$^\{\backslash$prime$\}$

$\backslash ]$

b$)$ Write gate level Verilog Description for $\backslash ($ F $\backslash )$

Q$2)(26$ points: $8+18)$

a$)$ The circuit shown below has $3$ inputs: $\backslash ($ a$,$ b $\backslash ),$ and $\backslash ($ c $\backslash ).$ Also it has one output $\backslash ($ d $\backslash ).$ The output $\backslash ($ d $\backslash )$ will be $1$ if exactly $2$ inputs are $1.$ Otherwise, output d will be $0.$ Write a Verilog code to describe this gate.

b$)$ The circuit shown below has $2$ inputs: a and cik and one output d

The output $"$ d $"$ is high when the input $"$ a $"$ has been high on exactly $2$ of the previous $3$ clock cycles. Otherwise, output $\backslash ($ d $\backslash )$ will be low. Write a Verilog code to describe this machine, and explain how your design works.