solve $1$ and $2$ with arm assembly $($not pseudocode or C$)$:

GLOBAL $\_\_$main

AREA main, CODE, READONLY

EXPORT $\_\_$main

EXPORT $\_\_$use$\_$two$\_$region$\_$memory

$\_\_$use$\_$two$\_$region$\_$memory EQU $0$

EXPORT SystemInit

EXPORT virtual$\_$gpio$\_$in

EXPORT virtual$\_$gpio$\_$out

ENTRY

GET BOARD.S

io$\_$delay EQU $3$

io$\_$len$\_1$ EQU $256$

; System Init routine

SystemInit

BX LR

;

$\_\_$main

;

LDR R$0,=$io$\_$data$\_1$

LDR R$1,=$virtual$\_$gpio$\_$in

LDR R$2,=$virtual$\_$gpio$\_$out

LDR R$3,=0$x$8$

LDR R$4,=$io$\_$delay

LDR R$5,=$io$\_$len$\_1$

BL edge$\_$detector$\_$reset

playback$\_$loop$\_1$

LDR R$6,[$R$0],$ #$4$

STR R$6,[$R$1]$

PUSH $\{$R$0-$R$6\}$

;

BL edge$\_$detector

;

POP $\{$R$0-$R$6\}$

BL delay

SUBS R$5,$ #$1$

BNE playback$\_$loop$\_1$

;

MOV R$6,$ #$0$

LDR R$5,=20$

fill$\_01$s

STR R$6,[$R$1]$

EOR R$6,$ #$0$xffffffff

SUBS R$5,$ #$1$

BNE fill$\_01$s

MOV R$6,$ #$0$

STR R$6,[$R$1]$

LDR R$0,=$io$\_$data$\_1$

LDR R$3,=0$x$200$

LDR R$5,=$io$\_$len$\_1$

BL edge$\_$detector$\_$reset

playback$\_$loop$\_2$

LDR R$6,[$R$0],$ #$4$

STR R$6,[$R$1]$

PUSH $\{$R$0-$R$6\}$

;

BL edge$\_$detector

;

POP $\{$R$0-$R$6\}$

BL delay

SUBS R$5,$ #$1$

BNE playback$\_$loop$\_2$

;

; Test 'calc$\_$pllcfg$\text{'}$

;

; Next $2$ inputs must return R$0=-1$ and R$1=0($wrong input parameter$)$

;

LDR R$1,=10000000$

BL calc$\_$pllcfg

;

LDR R$1,=200000000$

BL calc$\_$pllcfg

;

; Calculate M and P to run PLL at $36$ MHz$.$ Using PLLCFG$\_$MSEL$\_$xxx and PLLCFG$\_$PSEL$\_$xxx constants

; store P and M into R$2.$

; Use this number to check the output $($R$0)$ of your function.

;

; LDR R$2,=($PLLCFG$\_$MSEL$\_?$:OR:PLLCFG$\_$PSEL$\_?)$

;

;

; For all $3$ examples below, resulting actual CLK $($R$1)$ must be $36000000$

;

LDR R$1,=36000000$

BL calc$\_$pllcfg

;

LDR R$1,=37000000$

BL calc$\_$pllcfg

;

LDR R$1,=35000000$

BL calc$\_$pllcfg

;

; Calculate M and P to run PLL at $120$ MHz$.$ Using PLLCFG$\_$MSEL$\_$xxx and PLLCFG$\_$PSEL$\_$xxx constants

; store P and M into R$2.$

; Use this number to check the output $($R$0)$ of your function.

;

; LDR R$2,=($PLLCFG$\_$MSEL$\_?$:OR:PLLCFG$\_$PSEL$\_?)$

;

;

; For the example below, resulting actual CLK $($R$1)$ must be $120000000$

;

LDR R$1,=120000000$

BL calc$\_$pllcfg

;

stop

B stop ; Loop forever!

delay

PUSH $\{$R$4,$ LR$\}$

TEQ R$4,$ #$0$

delay$\_$loop

POPEQ $\{$R$4,$ PC$\}$

SUBS R$4,$ #$1$

B delay$\_$loop

;

; $1.$ Edge detector. Write a function that outputs a short pulse on bit $7$ of "virtual$\_$gpio$\_$out" when

; rising edge is detected on one of bit of "virtual$\_$gpio$\_$in$".$ The bit to detect the rising edge

; $($bit mask$)$ is passed via R$3.$ The 'rising edge' is changing bit from $\text{'}0\text{'}$ to $\text{'}1\text{'}.$

;

; Parameters:

; R$1-$ Address of "virtual$\_$gpio$\_$in$"$

; R$2-$ Address of "virtual$\_$gpio$\_$out"

; R$3-$ bit mask. The bit the 'rising edge' conditions should be detected for.

;

; Output:

; Bit $7$ if "virtual$\_$gpio$\_$out" should be set to $\text{'}1\text{'}$ when 'rising edge' is detected,

; Bit $7$ should be $\text{'}0\text{'}$ for all other conditions $($falling edge, stable $\text{'}1\text{'}$ or stable $\text{'}0\text{'}).$

;

edge$\_$detector

PUSH $\{$LR$\}$ ; You may need to modify this command

; $--$ Instructions of your function is here

POP $\{$PC$\}$ ; You may need to modify this command

;

; $1$a$.$ You may need one additional function to reset the 'edge detector'.

;

edge$\_$detector$\_$reset

PUSH $\{$LR$\}$ ; You may need to modify this command

; $--$ Instructions of your function is here

POP $\{$PC$\}$ ; You may need to modify this command

;

; $2.$ Write a function that calculates the PLLCFG register values $($P and M PLL parameters$)$

; for a given PLL output frequency.

;

; Input clock Frequency $-12$ MHz $($or $12000000$ Hz$)$

;

; Valid values for the PLL frequency are $12$ MHz $-120$ MHz$.$ The function must check the

; validity of the required frequency.

;

; If the preset frequency cannot be obtained, the function must set the nearest possible

; PLL frequency.

;

; Parameters:

;

; R$0=$ Output: PLLCFG value or $-1(0$xFFFFFFFF$)$ if required output frequency is not correct.

; R$1-$ Input: Required output PLL clock rate in Hz$.($So$,36000000$ is $36$ MHz$)$

; Output: Actual clock rate or $0$ if required output frequency is not correct.

;

; Preserve the values of any registers you are using in your function.

;

calc$\_$pllcfg

;

; $12$MHz $-120$MHz

;

; R$0=$ Output : PLLCFG value $(-1(0$xFFFFFFFF$)$ if input is not correct$)$

; R$1-$ Input $-$ required clock rate, Output $=$ actual clock rate. $(0$ if input is not correct$)$

;

; R$2-$ constant $120$MHz$,12$MHz$,156$ MHz

; R$3-$ M

; R$4-$ CLK $\%12$ MHz$,$ P$*2$

; R$5-$ constant $6$MHz$,320$ MHz

; R$6-$ working $($CLK $*2*$ P$)$

;

; $--$ Put your instructions here...

stop$\_$no$\_$function

B stop$\_$no$\_$function ; Loop forever!

ALIGN

LTORG

io$\_$data$\_1$

DCD $38456,38456,38456,38456,38456,38456,38456,38456,38456,5031$

DCD $5031,5031,5031,5031,5031,5031,5031,5031,45661,45661$

DCD $45661,45661,45661,45661,45661,45661,45661,45661,45661,45661$

DCD $45661,45661,45661,45661,45661,45661,45661,45661,24865,24865$

DCD $24865,24865,24865,24865,24865,24865,24865,24865,24865,13349$