SOLVE IT FOR ME USING VHDL CODE

Design a $4-$bit shift register and counter in a single VHDL design by implementing one process for each function: the shift

register and the counter. The design should meet the following specifications:

Inputs: The design should include $8$ inputs: sel, shift, clk$,$ load, Clear, Prest, Sin, and D$(3$:$0).$

Output: The design should have one output: Q$(3$:$0).$

Functionality:

Operates as a counter when sel $=1.$

Operates as a shift register when sel $=0,$ implemented using the when else statement.

The shift register$/$counter functions are defined in the following table: $[24$ Points$].$

Simulate your design for all different input combinations. $(16$ Points$-2$ pint for testing each input$)$