Someone proposes the following verilog code for a 3-to-1 multiplexor. What is the value of "out' when sel = "11''? Explain your input reasoning. Support your reasoning by writing a test fixture for mux 3 to 1and apply the following stimulus. Capture the waveform. Data = 3'b010 sel = 2'b11, 2'b00, 2'b10, 2'b11, 2'b01, 2'b11 Clearly this is a poorly written verilog code. Fix the code so that it truly reflects a 3-to-1 mux with out = X when sel = 2'b11. Rerun the test with the same test fixture and capture the waveform