Question: State whether these statements about reg and wire types in Verilog are True of False: (each question is 0. 1- reg can be connected to

State whether these statements about reg and wire types in Verilog are True of False: (each question is 0. 1- reg can be connected to the input port of a module instantiation. 2-wire is the only legal type on the left-hand side of an always@block - or

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