Stretch Activity

When performing computational operations it is often useful to be able to exe$-$

cute a sequence of operations, each one using the output of the previous step as

an input to the next step. For example to OR $3$ values X OR Y OR Z you might

first calculate X OR Y and then on the next step apply OR Z to the previous

output $($X OR Y $).$

For this task adapt the circuit FALL so that it can combine a sequence of

operations defined by different values for f$1$ and f$0$ at each step, by enabling

the outputs Ft and Gt of step t to be used $($feedback$)$ as the inputs for the next

operation Ct$+1$ and Dt$+1$ for step t $+1.$ You should also add a further input

$($Load$)$ to the chip which when Load $=1$ will enable you to load new inputs to

Ct and Dt and when set to $0$ sets Ct$+1=$ Ft and Dt$+1=$ Gt$.$ The Load input

will allow you to manually set the values of C and D at the start and during

the sequence if required.

Call this chip FSEQ. You can test this chip using FSEQ.tst but may wish to

create further tests before submission.

You must only use the built$-$in AND, NAND, OR$,$ NOR, NOT, Mux, DMux,

XOR or DFF chips.

Here is my chip FSEQ: CHIP FSEQ $\{$

IN A$,$ B$,$ C$,$ D$,$ f$0,$ f$1,$ load;

OUT E$,$ F$,$ G$,$ Ft$,$ Gt;

PARTS:

FZero$($A$=$A$,$ B$=$B$,$ C$=$C$,$ D$=$D$,$ F$=$outF$0,$ G$=$outG$0)$;

FOne$($A$=$A$,$ B$=$B$,$ C$=$C$,$ D$=$D$,$ F$=$outF$1,$ G$=$outG$1)$;

FTwo$($A$=$A$,$ B$=$B$,$ C$=$C$,$ D$=$D$,$ F$=$outF$2,$ G$=$outG$2)$;

FThree$($A$=$A$,$ B$=$B$,$ C$=$C$,$ D$=$D$,$ E$=$outE$3,$ F$=$outF$3,$ G$=$outG$3)$;

Mux$($a$=$outE$3,$ b$=$false, sel$=$f$0,$ out$=$EMux$1)$;

Mux$($a$=$EMux$1,$ b$=$false, sel$=$f$1,$ out$=$E$)$;

Mux$($a$=$outF$3,$ b$=$outF$2,$ sel$=$f$0,$ out$=$FMux$1)$;

Mux$($a$=$outF$1,$ b$=$outF$0,$ sel$=$f$0,$ out$=$FMux$2)$;

Mux$($a$=$FMux$1,$ b$=$FMux$2,$ sel$=$f$1,$ out$=$F$)$;

Mux$($a$=$outG$3,$ b$=$outG$2,$ sel$=$f$0,$ out$=$GMux$1)$;

Mux$($a$=$outG$1,$ b$=$outG$0,$ sel$=$f$0,$ out$=$GMux$2)$;

Mux$($a$=$GMux$1,$ b$=$GMux$2,$ sel$=$f$1,$ out$=$G$)$;

DFF$($in$=$nextC, out$=$currentC$)$;

DFF$($in$=$nextD, out$=$currentD$)$;

Mux$($a$=$A$,$ b$=$currentC, sel$=$load, out$=$nextC$)$;

Mux$($a$=$B$,$ b$=$currentD, sel$=$load, out$=$nextD$)$;

Mux$($a$=$currentC, b$=$nextC, sel$=$load, out$=$Ft$)$;

Mux$($a$=$currentD, b$=$nextD, sel$=$load, out$=$Gt$)$;

$\}$

However, it is not passing the following test file FSEQ.tst:

load FSEQ.hdl$,$

output$-$file FSEQ.out,

compare$-$to FSEQ.cmp$,$

output$-$list f$1\%$B$3\mathrm{.}1\mathrm{.}3$ f$0\%$B$3\mathrm{.}1\mathrm{.}3$ A$\%$B$3\mathrm{.}1\mathrm{.}3$ B$\%$B$3\mathrm{.}1\mathrm{.}3$ C$\%$B$3\mathrm{.}1\mathrm{.}3$ D$\%$B$3\mathrm{.}1\mathrm{.}3$ E$\%$B$3\mathrm{.}1\mathrm{.}3$ F$\%$B$3\mathrm{.}1\mathrm{.}3$ G$\%$B$3\mathrm{.}1\mathrm{.}3$;

set load $1,$

set f$11,$

set f$01,$

set A $1,$

set B $0,$

set C $1,$

set D $1,$

tick,

tock,

output;

set load $0,$

set f$10,$

set f$00,$

tick,

tock,

output;

set f$11,$

set f$01,$

tick,

tock,

output;

Please help me to fix my chip so that it passes this test. You can test the file with the hardware simulator on nand$2$tetris.com Below is FSEQ.cmp:

$|$ f$1|$ f$0|$ A $|$ B $|$ C $|$ D $|$ E $|$ F $|$ G $|$

$|1|1|1|0|1|1|0|0|0|$

$|0|0|1|0|1|1|0|1|0|$

$|1|1|1|0|1|1|0|0|1|$