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Question $6-[25$ Marks$]$ Processor Design.

The datapath of the multi$-$cycle processor we described in the lectures is given on the next page. The diagram includes additional detail. We are to modify the SUB instruction to TEST&SET R$1($R$2)$ which does the following:

$RE[$ Inst $7,6]=$MEM$[RF[$ Inst$5,4]]$

MEM$[RF[5,4]]=0FFF$

$PC=PC+1$

In words:

write in register $R1$ the value from the memory address pointed by the register $R2,$ and then write $0xFF$ into the aforementioned memory address.

a$)$ Below write the actions that the datapath needs to tate per cycle to implement the instruction. The table lists the the first two cycles.

$\backslash$table$[[$CYCLE$,$Actions$],[1,\backslash$table$[[$IR $=$ Mem$[$PC$]],[$PC $=PC+1$

$-$final$-2021.$pdf

$(4)$

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al$-2021.$pdf

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c$)$ Show how this instruction can be implemented by listing the values for the control signals. Add any new control signals in the empty rows.