Suppose processor X executes instructions in the following $4-$ stages $($no pipeline$),$ where each stages could run this fast. $15$ Marks$]$ F$10$ EX $15$ns $10$ns MEM $20$ns WB Sns a$)$ What is the approximate speedup of the $4-$stage pipeline in the steady state under ideal conditions as compared to the corresponding non$-$pipelined implementation? Also, give the theoretical maximum speedup for this pipeline. b$)$ Now assume that $20\%$ of the instructions are load$/$store instructions. The remaining instructions do not need to execute the MEM stage. What is the approximate speedup of the $4$ stage pipeline as compared to the corresponding non$-$pipelined implementation?