Suppose that a task on the ARM computer runs 128,000,000 (128M) instructions during its execution. The total time it takes to execute an instruction is 100 ns, independent of the clock cycle time. We make the assumption that the work to be performed by one instruction can be divided into arbitrary number of pipeline stages. Now complete the following problems.

Complete the table by computing the stage time, total execution time, and speedup (relative to the non-pipelined case) for the different pipelining depths. Ignore all hazards. Neglect stage time increases caused by pipeline register delays, etc., for this part.

Pipeline depth	Stage time	Total execution time	Speedup
1	100ns		1
2
4
8

Now suppose that the pipelining register delays and processor control overhead adds 20ns to the latency of each pipeline stage. (So, for example, if there are four pipeline stages, each instruction will have an execution latency of 180ns and the pipelined machine produces 1 instruction every 45ns.) What is the maximum speedup that can be obtained through pipelining? Assume there are no hazards (ideal pipelining)

Now consider the possible stalls caused by hazards in the pipeline. Complete the table below using the average stall cycles per instruction listed for each pipeline depth. Ignore stage time increases caused by pipeline register delays, control overhead, etc., for this part. List your major calculation steps for each row so that you can get as much credit as possible.

Pipeline depth	Average number of stall cycles per instruction	Stage time	Total execution time	Speedup
1	0	100ns		1
2	0.6
4	1.4
8	4