suppose we have two implementations of the same instruction set architecture. computer A has a clock rate of $4GHz$ and a $\frac{C}{P}$I of $4\mathrm{.}0$ for same program. computer $B$ has a clock rate of $5GHz$ and a $\frac{C}{P}$I of $2\mathrm{.}5$ for the same program. the CPU time for program B equals:

$4$ I nseconds

$2\mathrm{.}5$ Inseconds

$1$ Inseconds

$0\mathrm{.}5$ Inseconds

Assum you have a a $3GHz,$ five$-$stage pipeline, such a processor would have $*$