Question: Suppose you are designing a processor with 48bits address bus and 64 bits' data bus. Memory is byte! addressable. a) [1.5 Points) If you wanted

Suppose you are designing a processor with 48bits address bus and

Suppose you are designing a processor with 48bits address bus and 64 bits' data bus. Memory is byte! addressable. a) [1.5 Points) If you wanted to implement an 2M words fully associative Ll cache, show the sizes of the different fields in this Ll cache. Indicate the number of rows in cache

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