Suppose you have a multi$-$core processor where each core has a local data cache without cache coherence support. The data cache on each processor uses a write$-$back policy. Suppose that the cache uses block sizes of two words $($say $8$ bytes$)$ and we have two word$-$size variables, X$,$ and X$\text{'},$ which are located in adjacent, word$-$aligned memory addresses, and in the same block. Suppose that the following sequence of events happens on two different processor cores, A and B: